Перевод названия: Double-pipelined architecture of a real-time recurrent noise filtering
Тип публикации: статья из журнала
Год издания: 2018
Идентификатор DOI: 10.18127/j20700784-201812-23
Ключевые слова: конвейерная обработка сигналов, плис, фильтрация помех, pipeline signal processing, Fpga, interference filtering
Аннотация: Приведено исследование способа двойной конвейеризации для аппаратной реализации рекуррентного алгоритма фильтрации сигнала фазированной антенной решетки от помех. In this paper, a real-time noise filtering architecture is investigated. Several aspects of the noise filtering algorithm implemented in the hardware has described. CompaПоказать полностьюred to a standard compute architecture of a recurrent solving algorithm the proposed architecture have performance and computation speed-up advantages. Based idea of the novel architecture is an augmentation of a general compute architecture by the simple function calculus for prediction. This prediction functions does extrapolation in a linear region of the filter coefficients convergence graph. The prediction functions is a simpler in a computation sense than a filter coefficients computa-tion block. Therefore, while computation block is busy by a computing at non-linear region a prediction block does a several compute iterations to the new non-linear region of the filter coefficients convergence graph. To get a uniform behavior of a filter coefficients calculation the second background compute pipeline is added. When a first compute pipeline result will ready the second compute pipeline is started to compute filter coefficients with new parameters. The simulation of a double-pipelined architecture has a signifi-cant advantages in a speed of a convergence to the optimal filter coefficients values.
Журнал: Успехи современной радиоэлектроники
Выпуск журнала: № 12
Номера страниц: 112-115
ISSN журнала: 20700784
Место издания: Москва
Издатель: Закрытое акционерное общество Издательство Радиотехника